Wednesday, October 2, 2013
8:30 a.m. to 5:00 p.m.
Level 0 auditorium between Ibn Al-Haytham and Ibn Sina (buildings 2 and 3)
The largest chip manufacturer Intel will be coming to co-present with the KAUST Supercomputing Lab, a one-day workshop about accelerating scientific applications using the latest hardware technology: the Intel Xeon Phi.
Registration is free but required. To register, please complete the online registration form.
For more information about the venue, registration, and the (tentative) agenda, please visit http://www.hpc.kaust.edu.sa/training/2013/Phi.
Exascale machines will flourish by the end of this decade resulting in complex systems with a concurrency of billion threads. Today, a single Intel Xeon Phi can sit under your desk with tens of cores and can deliver out more than 1 Tflop/s. This already requires end-users to rethink and redesign their algorithms to take advantage of the underlying architecture while keeping productivity in mind.
The tutorial is intended to provide participants an overview on the new Intel Xeon Phi coprocessor, also known as Intel Many Integrated Core (MIC). Even-tough the MIC is an x86 based coprocessor and the execution of most user codes is enabled with little porting effort, the MIC architecture has significant features that are different from that of present x86 CPUs, and getting decent performance often requires an understanding of the possible execution models and basic details of the architecture.
This tutorial will present an introduction and give an overview of the Intel Xeon Phi architecture. Technical sessions will describe the OpenMP programming model and show examples of scientific codes ported on the MIC architecture. Some of the current supported software packages will be also highlighted.
Come and learn how to boost the performance of your existing application! The targeted audience is beginner to intermediate.
Hatem Ltaief, Workshop Chair
Saber Feki, Workshop Co-Chair
Bilel Hadri, Workshop Co-Chair
